#ifndef __HOBOT_PM_H__
#define __HOBOT_PM_H__

#define  DDRP_BASE_PA          (0xA2000000)
#define  DDRP_ADDR_SIZE        (0xF00000)
#define  DDRC_BASE_PA          (0xA2D00000)
#define  DDRC_ADDR_SIZE        (0x1000)
#define  SYSCTRL_BASE_PA       (0xA1000000)
#define  SYSCTRL_ADDR_SIZE     (0x700)
#define X2_PMU_BASE_PA         (0xA6000000)
#define X2_PMU_ADDR_SIZE       (0x304)
#define X2_PADC_BASE_PA        (0xA6003000)
#define X2_PADC_ADDR_LEN       (0x204)

#define WAKEUP_SRC_PADC_EXT	1
#define WAKEUP_SRC_RTC		2

#define X2_PMU_SLEEP_PERIOD             (0x0000)
#define X2_PMU_SLEEP_CMD                (0x0004)
#define X2_PMU_WAKEUP_STA               (0x0008)
#define X2_PMU_OUTPUT_CTRL              (0x000C)
#define X2_PMU_VDD_CNN_CTRL             (0x0010)
#define X2_PMU_DDRSYS_CTRL              (0x0014)

#define X2_PMU_W_SRC                    (0x0030)
#define X2_PMU_W_SRC_MASK               (0x0040)

#define X2_PMU_SW_REG_00                (0x0200)
#define X2_PMU_SW_REG_01                (0x0204)
#define X2_PMU_SW_REG_02                (0x0208)
#define X2_PMU_SW_REG_03                (0x020c)
#define X2_PMU_SW_REG_04                (0x0210)
#define X2_PMU_SW_REG_05                (0x0214)
#define X2_PMU_SW_REG_06                (0x0218)
#define X2_PMU_SW_REG_27                (0x026c)
#define X2_PMU_SW_REG_28                (0x0270)
#define X2_PMU_SW_REG_29                (0x0274)
#define X2_PMU_SW_REG_30                (0x0278)
#define X2_PMU_SW_REG_31                (0x027c)


#define	SLEEP_PERIOD		0x80000000
#define WAKEUP_SOURCE_MASK	0xfc
#define SLEEP_TRIG		0x1
#define CLK_HZ		32768

#define WAKEUP_PIN_REG		0x70
#define WAKEUP_PIN_CFG		0xC000


#define X2_DDRSYS_CLKEN_CLR             (0x138)


#define DDRP_APBONLY0_MICROCONTMUXSEL   0x340000
#define DDRP_DRTUB0_UCCLKHCLKENABLES    0x300200
#define DDRP_INITENG0_PHYINLP3          0x2400a0



/* ddr controller registers */
#define DDRC_MSTR             (0x00)
#define DDRC_STAT             (0x04)
#define DDRC_MSTR1            (0x08)
#define DDRC_MRCTRL0          (0x10)
#define DDRC_MRCTRL1          (0x14)
#define DDRC_MRSTAT           (0x18)
#define DDRC_MRCTRL2          (0x1c)
#define DDRC_DERATEEN         (0x20)
#define DDRC_DERATEINT        (0x24)
#define DDRC_DERATECTL        (0x2c)
#define DDRC_PWRCTL           (0x30)
#define DDRC_PWRTMG           (0x34)
#define DDRC_HWLPCTL          (0x38)
#define DDRC_HWFFCCTL         (0x3c)
#define DDRC_HWFFCSTAT        (0x40)
#define DDRC_RFSHCTL0         (0x50)
#define DDRC_RFSHCTL1         (0x54)
#define DDRC_RFSHCTL2         (0x58)
#define DDRC_RFSHCTL3         (0x60)
#define DDRC_RFSHTMG          (0x64)
#define DDRC_RFSHTMG1         (0x68)
#define DDRC_ECCCFG0          (0x70)
#define DDRC_ECCCFG1          (0x74)
#define DDRC_ECCSTAT          (0x78)
#define DDRC_ECCCLR           (0x7c)
#define DDRC_ECCERRCNT        (0x80)
#define DDRC_ECCCADDR0        (0x84)
#define DDRC_ECCCADDR1        (0x88)
#define DDRC_ECCCSYN0         (0x8c)
#define DDRC_ECCCSYN1         (0x90)
#define DDRC_ECCCSYN2         (0x94)
#define DDRC_ECCBITMASK0      (0x98)
#define DDRC_ECCBITMASK1      (0x9c)
#define DDRC_ECCBITMASK2      (0xa0)
#define DDRC_ECCUADDR0        (0xa4)
#define DDRC_ECCUADDR1        (0xa8)
#define DDRC_ECCUSYN0         (0xac)
#define DDRC_ECCUSYN1         (0xb0)
#define DDRC_ECCUSYN2         (0xb4)
#define DDRC_ECCPOISONADDR0   (0xb8)
#define DDRC_ECCPOISONADDR1   (0xbc)
#define DDRC_CRCPARCTL0       (0xc0)
#define DDRC_CRCPARCTL1       (0xc4)
#define DDRC_CRCPARCTL2       (0xc8)
#define DDRC_CRCPARSTAT       (0xcc)
#define DDRC_INIT0            (0xd0)
#define DDRC_INIT1            (0xd4)
#define DDRC_INIT2            (0xd8)
#define DDRC_INIT3            (0xdc)
#define DDRC_INIT4            (0xe0)
#define DDRC_INIT5            (0xe4)
#define DDRC_INIT6            (0xe8)
#define DDRC_INIT7            (0xec)
#define DDRC_DIMMCTL          (0xf0)
#define DDRC_RANKCTL          (0xf4)
#define DDRC_DRAMTMG0         (0x100)
#define DDRC_DRAMTMG1         (0x104)
#define DDRC_DRAMTMG2         (0x108)
#define DDRC_DRAMTMG3         (0x10c)
#define DDRC_DRAMTMG4         (0x110)
#define DDRC_DRAMTMG5         (0x114)
#define DDRC_DRAMTMG6         (0x118)
#define DDRC_DRAMTMG7         (0x11c)
#define DDRC_DRAMTMG8         (0x120)
#define DDRC_DRAMTMG9         (0x124)
#define DDRC_DRAMTMG10        (0x128)
#define DDRC_DRAMTMG11        (0x12c)
#define DDRC_DRAMTMG12        (0x130)
#define DDRC_DRAMTMG13        (0x134)
#define DDRC_DRAMTMG14        (0x138)
#define DDRC_DRAMTMG15        (0x13C)
#define DDRC_DRAMTMG16        (0x140)
#define DDRC_DRAMTMG17        (0x144)
#define DDRC_ZQCTL0           (0x180)
#define DDRC_ZQCTL1           (0x184)
#define DDRC_ZQCTL2           (0x188)
#define DDRC_ZQSTAT           (0x18c)
#define DDRC_DFITMG0          (0x190)
#define DDRC_DFITMG1          (0x194)
#define DDRC_DFILPCFG0        (0x198)
#define DDRC_DFILPCFG1        (0x19c)
#define DDRC_DFIUPD0          (0x1a0)
#define DDRC_DFIUPD1          (0x1a4)
#define DDRC_DFIUPD2          (0x1a8)
#define DDRC_DFIMISC          (0x1b0)
#define DDRC_DFITMG2          (0x1b4)
#define DDRC_DFITMG3          (0x1b8)
#define DDRC_DFISTAT          (0x1bc)
#define DDRC_DBICTL           (0x1c0)
#define DDRC_DFIPHYMSTR       (0x1c4)
#define DDRC_TRAINCTL0        (0x1d0)
#define DDRC_TRAINCTL1        (0x1d4)
#define DDRC_TRAINCTL2        (0x1d8)
#define DDRC_TRAINSTAT        (0x1dc)
#define DDRC_ADDRMAP0         (0x200)
#define DDRC_ADDRMAP1         (0x204)
#define DDRC_ADDRMAP2         (0x208)
#define DDRC_ADDRMAP3         (0x20c)
#define DDRC_ADDRMAP4         (0x210)
#define DDRC_ADDRMAP5         (0x214)
#define DDRC_ADDRMAP6         (0x218)
#define DDRC_ADDRMAP7         (0x21c)
#define DDRC_ADDRMAP8         (0x220)
#define DDRC_ADDRMAP9         (0x224)
#define DDRC_ADDRMAP10        (0x228)
#define DDRC_ADDRMAP11        (0x22c)
#define DDRC_ODTCFG           (0x240)
#define DDRC_ODTMAP           (0x244)
#define DDRC_SCHED            (0x250)
#define DDRC_SCHED1           (0x254)
#define DDRC_PERFHPR1         (0x25c)
#define DDRC_PERFLPR1         (0x264)
#define DDRC_PERFWR1          (0x26c)
#define DDRC_PERFVPR1         (0x274)
#define DDRC_PERFVPW1         (0x278)
#define DDRC_DQMAP0           (0x280)
#define DDRC_DQMAP1           (0x284)
#define DDRC_DQMAP2           (0x288)
#define DDRC_DQMAP3           (0x28c)
#define DDRC_DQMAP4           (0x290)
#define DDRC_DQMAP5           (0x294)
#define DDRC_DBG0             (0x300)
#define DDRC_DBG1             (0x304)
#define DDRC_DBGCAM           (0x308)
#define DDRC_DBGCMD           (0x30c)
#define DDRC_DBGSTAT          (0x310)
#define DDRC_SWCTL            (0x320)
#define DDRC_SWSTAT           (0x324)
#define DDRC_OCPARCFG0        (0x330)
#define DDRC_OCPARCFG1        (0x334)
#define DDRC_OCPARCFG2        (0x338)
#define DDRC_OCPARCFG3        (0x33c)
#define DDRC_OCPARSTAT0       (0x340)
#define DDRC_OCPARSTAT1       (0x344)
#define DDRC_OCPARWLOG0       (0x348)
#define DDRC_OCPARWLOG1       (0x34c)
#define DDRC_OCPARWLOG2       (0x350)
#define DDRC_OCPARAWLOG0      (0x354)
#define DDRC_OCPARAWLOG1      (0x358)
#define DDRC_OCPARRLOG0       (0x35c)
#define DDRC_OCPARRLOG1       (0x360)
#define DDRC_OCPARARLOG0      (0x364)
#define DDRC_OCPARARLOG1      (0x368)
#define DDRC_POISONCFG        (0x36C)
#define DDRC_POISONSTAT       (0x370)

#define DDRC_PSTAT            (0x3fc)
#define DDRC_PCCFG            (0x400)
#define DDRC_PCTRL_0          (0x490)
#define DDRC_PCTRL_1          (0x490 + 1 * 0xb0)
#define DDRC_PCTRL_2          (0x490 + 2 * 0xb0)
#define DDRC_PCTRL_3          (0x490 + 3 * 0xb0)
#define DDRC_PCTRL_4          (0x490 + 4 * 0xb0)
#define DDRC_PCTRL_5          (0x490 + 5 * 0xb0)
#define DDRC_PCFGW_0          (0x408)
#define DDRC_PCFGW_1          (1 * 0xb0 + 0x408)
#define DDRC_PCFGW_2          (2 * 0xb0 + 0x408)
#define DDRC_PCFGW_3          (3 * 0xb0 + 0x408)
#define DDRC_PCFGW_4          (4 * 0xb0 + 0x408)
#define DDRC_PCFGW_5          (5 * 0xb0 + 0x408)

#define DDRC_PCFGC_0          (0x40c)
#define DDRC_PCFGIDMASKCH     (0x410)
#define DDRC_PCFGIDVALUECH    (0x414)
#define DDRC_PCTRL_0          (0x490)
#define DDRC_PCTRL_1          (0x490 + 1 * 0xb0)
#define DDRC_PCTRL_2          (0x490 + 2 * 0xb0)
#define DDRC_PCTRL_3          (0x490 + 3 * 0xb0)
#define DDRC_PCTRL_4          (0x490 + 4 * 0xb0)
#define DDRC_PCTRL_5          (0x490 + 5 * 0xb0)



#endif /* __HOBOT_PM_H__ */
